Advances in silicon technology increasingly allow larger and more complex designs of electronic circuits to be formed on a single chip. For example, modern electronic designs have millions or tens of millions of transistors. At the same time, market demands push circuit designers to create these designs rapidly and efficiently. A recent trend to increase the speed and efficiency of the design process involves the re-use, or recycling, of electronic circuit blocks or subsystems, commonly referred to as cores, Intellectual Properties (IPs), or virtual component blocks (VCs). Once the design for a virtual component block has been tested and verified, it can be re-used in other applications that may be completely distinct from the application which led to its original creation.
For example, a subsystem for a cellular phone application specific integrated circuit (ASIC) may contain a micro-controller, a digital signal processor, and other electronic components. After the design for the cellular phone subsystem has been tested and verified, it could be re-used as a virtual component block in a circuit design for an automotive application. The reuse of virtual component blocks allows a designer to complete the design process much faster than building the entire design from scratch, and avoids the need for debugging, testing and verification of the subsystems embodied in the virtual component block.
While virtual components have been found to be convenient for expediting and simplifying the circuit design process, the successful use of virtual component blocks hinges on the ability of the designer to accurately characterize their timing and functionality. A number of techniques have been proposed and developed for performing timing analyses on virtual component blocks, among which static timing analysis (STA) is most widely used.
Static Timing Analysis is used in the process of verifying the timing correctness of a digital circuit design during one clock cycle, without the need for simulating the circuit. During the STA process, a worst-case structural (or topological) delay between a circuit's inputs and outputs is calculated. For example, a model of a signal that propagates through combinational logic includes an analysis of the longest and the shortest paths spanning between a launching register and a capturing register in order to determine, in the worst case, whether the signal arrives at the capturing register during the active pulse of the clock cycle.
In STA, a rising or falling voltage transition is abstracted by a timing event (TE), to approximate the transition of the actual waveform using two of its parameters, the arrival time and slew rate. The arrival time of the transition is based on the time that the voltage of the waveform reached a user-selected reference voltage (Vref), or trip point, such as 0.5Vdd for example. The slew rate is determined by an amount of time for the waveform to move from one given voltage level, Vth1, to a second given voltage, Vth2. For example, the slew rate may be based on the amount of time that the waveform takes to transition from a voltage of 0.2Vdd to 0.8Vdd. However, given the complexity of modem designs, the approximation of the waveform provided by the TE may be insufficient to verify the design's timing correctness.
For example, in a STA process, a design is represented by an acyclic directed graph, called a Timing Graph (TG), where timing nodes represent intermediate in the design and edges represent delays along nets and library cells. The TG is built using an assumption that the delay through a given stage is dependent only on the waveform that is received by the stage, and on the interconnects of the stage. During the analysis, TEs are propagated forward in the TG from input nodes to output nodes. If a stage has multiple inputs, the corresponding node in the TG receives multiple TEs. A worst-case TE is selected from the multiple TEs at the timing node for further propagation to downstream logic elements during the analysis.
In this conventional approach, only the arrival time of the timing event at the given node is used as the criterion for selecting the worst-case timing event, and the slew rate is typically not considered. However, ignoring the slew rate can lead to optimistic results for the critical path delay that is verified during this process, especially if a skewed gate (a gate with a trip point away from 0.5Vdd) is used. For example, a TE may be selected as the worst-case according to the conventional approach, which is based on the arrival time of the TE on the particular node. However, this “worst-case” TE may not be the worst-case TE if the TEs are propagated to the output of a skewed receiver, because the slew differences of the signals may have a strong impact on the delay over the receiving stage.
To prevent optimistic results, conventional tools [CTEref] allow a user to construct a new timing event by combining the worst arrival time, (such as the maximum time for a max delay analysis or the minimum time for min delay analysis) and the worst slew rate (such as the lowest or highest slew rate for, respectively, max or min delay analysis). The arrival time and slew rate of the new “worst-case” timing event is therefore a combination of various parts of different timing events, rather than a selection of one of the TEs that arrives at the receiving gate. While this approach is usually conservative, it may lead to optimistic results if the receiving gate is skewed. For example, if an inverter is skewed towards a low voltage (e.g. with similar sizes of p- and n-devices), a rising transition with a lower slew rate can result in a lower delay over the inverter.
Furthermore, the conventional analysis does not consider properties of the receiving gate itself when determining the worst-case transition. This causes results based on conventional criteria to be either optimistic or very conservative, and may lead to functional failures or over design.
Therefore, more accurate timing verification methods are needed. [ICCAD ref].